The invention relates to an integrated circuit comprising a dynamic CMOS Programmable Logic Array with an AND plane and an OR plane, the AND plane comprising a first matrix of first row lines and first column lines, the first column lines comprising 2n bit lines derived from n inputs, and the first row lines comprising m product lines, each product line being accompanied with a corresponding adjacent first evaluate line, the bit lines controlling first crosspoint transistors connecting product lines to corresponding first evaluate lines, the OR plane comprising a second matrix of second row lines and second column lines, the second row lines comprising m product term lines and the second column lines comprising k sum lines feeding k outputs, each sum line being accompanied with a corresponding adjacent second evaluate line, the product term lines controlling second crosspoint transistors connecting sum lines to corresponding second evaluate lines, each product term line corresponding to a respective product line, the product lines and the sum lines forming a set of precharge lines.
The invention further relates to a method for testing an integrated circuit comprising a dynamic CMOS Programmable Logic Array with an AND plane and an OR plane.
The Programmable Logic Array (PLA) is an important building block for VLSI circuits. It is commonly used in the design of instruction decoders of microprocessors, and combinational circuitry of finite state machines. The widespread use of the PLA is due to its simple architecture and availability of programs to automate the synthesis process. Dynamic PLAs are preferred compared to their static counterparts due to smaller area, low power dissipation and the ability to pipeline the processing for increased throughput.
In spite of their merits, PLAs are notorious for poor testability. Built In Self Test (BIST) schemes have been devised for functional testing of PLAs. However, these test schemes normally entail a large number of extra gates and test vectors. A second drawback is that implementation of these test schemes often heavily depends on the function implemented in the PLA, which leads to extra steps in the design process. A third drawback is that the known test schemes do not enable explicit testing for bridging faults between nodes. A bridging fault is formed by an unintended conductive bridge of low resistance. For circuits as specified in the preamble, bridging faults are particularly relevant in view of the large number of interconnections and densely packed lines. It has been found that, under the special circumstances of testing, a considerable amount of such defects are not detected by functional testing.